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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the MAX8741/max8742 are buck-topology, step-down, switch-mode, power-supply controllers that generate logic-supply voltages in battery-powered systems. these high-performance, dual/triple-output devices include on- board power-up sequencing, power-good signaling with delay, digital soft-start, secondary winding control, low- dropout circuitry, internal frequency-compensation net- works, and automatic bootstrapping. up to 97% efficiency is achieved through synchronous rectification and maxim? proprietary idle mode control scheme. efficiency is greater than 80% over a 1000:1 load-current range, which extends battery life in system suspend or standby mode. excellent dynamic response corrects output load transients within five clock cycles. strong 1a on-board gate drivers ensure fast external n-channel mosfet switching. these devices feature a logic-controlled and synchroniz- able, fixed-frequency, pulse-width-modulation (pwm) operating mode. this reduces noise and rf interference in sensitive mobile communications and pen-entry appli- cations. asserting the skip pin enables fixed-frequency mode, for lowest noise under all load conditions. the MAX8741/max8742 include two pwm regulators, adjustable from 2.5v to 5.5v with fixed 5.0v and 3.3v modes. all these devices include secondary feedback regulation, and the max8742 contains a 12v/120ma lin- ear regulator. the MAX8741 includes a secondary feed- back input (secfb), plus a control pin (steer) that selects which pwm (3.3v or 5v) receives the secondary feedback signal. secfb provides a method for adjusting the secondary winding voltage regulation point with an external resistor-divider, and is intended to aid in creating auxiliary voltages other than fixed 12v. the MAX8741/max8742 contain internal output overvolt- age- and undervoltage-protection features. ________________________applications notebook and subnotebook computers pdas and mobile communicators desktop cpu local dc-dc converters features ? 97% efficiency ? 4.2v to 30v input range ? 2.5v to 5.5v dual adjustable outputs ? selectable 3.3v and 5v fixed or adjustable outputs (dual mode) ? 12v linear regulator ? adjustable secondary feedback (MAX8741) ? 5v/50ma linear-regulator output ? precision 2.5v reference output ? programmable power-up sequencing ? power-good ( reset ) output ? output overvoltage protection ? output undervoltage shutdown ? 333khz/500khz low-noise, fixed-frequency operation ? low-dropout, 98% duty-factor operation ? 2.5mw typical quiescent power (12v input, both smpss on) ? 4? typical shutdown current MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ________________________________________________________________ maxim integrated products 1 5v linear 12v linear power-up sequence power- good 3.3v smps 5v smps reset on/off 5v (rtc) 3.3v input 5v 12v functional diagram 19-3262; rev 0; 4/04 ordering information idle mode is a trademark of maxim integrated products, inc. dual mode is a trademark of maxim integrated products, inc. pin configurations appear at end of data sheet. part temp range pin-package MAX8741 eai -40 c to +85 c 28 ssop MAX8741etj -40 c to +85 c 32 thin qfn 5m m x 5m m max8742 eai -40 c to +85 c 28 ssop max8742etj -40 c to +85 c 32 thin qfn 5m m x 5m m
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = 15v, both pwms on, sync = v l , v l load = 0, ref load = 0, skip = 0, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +36v pgnd to gnd.....................................................................?.3v v l to gnd ................................................................-0.3v to +6v bst3, bst5 to gnd ..............................................-0.3v to +36v csh3, csh5 to gnd................................................-0.3v to +6v fb3 to gnd ..............................................-0.3v to (csl3 + 0.3v) fb5 to gnd ...............................................-0.3v to (csl5 +0.3v) lx3 to bst3..............................................................-6v to +0.3v lx5 to bst5..............................................................-6v to +0.3v ref, sync, seq, steer, skip , time/on5, secfb, reset to gnd ..........-0.3v to (v l + 0.3v) v dd to gnd. ...........................................................-0.3v to +20v run/on3, shdn to gnd.............................-0.3v to (v+ + 0.3v) 12out to gnd ..........................................-0.3v to (v dd + 0.3v) dl3, dl5 to pgnd........................................-0.3v to (v l + 0.3v) dh3 to lx3 ..............................................-0.3v to (bst3 + 0.3v) dh5 to lx5 ..............................................-0.3v to (bst5 + 0.3v) v l , ref short to gnd ................................................momentary 12out short to gnd..................................................continuous ref current...........................................................+5ma to -1ma v l current.........................................................................+50ma 12out current . .............................................................+200ma v dd shunt current. ...........................................................+15ma continuous power dissipation (t a = +70?) 28-pin ssop (derate 9.52mw/? above +70?) ........762mw 32-pin thin qfn (derate 21.3mw/? above +70?) ....1702mw operating temperature range ...........................-40? to +85? storage temperature range ............................-65? to +160? lead temperature (soldering, 10s) ................................+300? parameter conditions min typ max units main smps controllers input voltage range 4.2 30.0 v 3v output voltage in adjustable mode v+ = 4.2v to 30v, csh3 - csl3 = 0, csl3 connected to fb3 2.42 2.5 2.58 v 3v output voltage in fixed mode v+ = 4.2v to 30v, 0 < csh3 - csl3 < 80mv, fb3 = 0 3.20 3.39 3.47 v 5v output voltage in adjustable mode v+ = 4.2v to 30v, csh5 - csl5 = 0, csl5 connected to fb5 2.42 2.5 2.58 v 5v output voltage in fixed mode v+ = 5.3v to 30v, 0 < csh5 - csl5 < 80mv, fb5 = 0 4.85 5.13 5.25 v output voltage adjust range either smps ref 5.5 v adjustable-mode threshold voltage dual-mode comparator 0.5 1.1 v load regulation either smps, 0 < csh_ - csl_ < 80mv -2 % line regulation either smps, 5.2v < v+ < 30v 0.03 %/v csh3 - csl3 or csh5 - csl5 80 100 120 current-limit threshold skip = v l or v dd < 13v or secfb < 2.44v -50 -100 -150 mv idle-mode threshold skip = 0, not tested 10 25 40 mv soft-start ramp time from enable to 95% full current limit with respect to f osc (note 1) 512 clks sync = v l 450 500 550 oscillator frequency sync = 0 283 333 383 khz
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 15v, both pwms on, sync = v l , v l load = 0, ref load = 0, skip = 0, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units sync = v l 95 97 maximum duty factor sync = 0 (note 2) 96.5 98 % sync input high pulse width not tested 200 ns sync input low pulse width not tested 200 ns sync rise/fall time not tested 200 ns sync input-frequency range 400 583 khz current-sense input leakage current v+ = v l = 0, csl3 = csh3 = csl5 = csh5 = 5.5v 0.01 10 ? flyback controller v dd regulation threshold falling edge (max8742) 13 14 v secfb regulation threshold falling edge (MAX8741) 2.44 2.60 v dl pulse width v dd < 13v or secfb < 2.44v 0.75 ? v dd shunt threshold rising edge, hysteresis = 1% (max8742) 18 20 v v dd shunt sink current v dd = 20v (max8742) 10 ma v dd leakage current v dd = 5v, off mode (note 3) 30 ? 12v linear regulator (max8742) 12out output voltage 13v < v dd < 18v, 0 < i load < 120ma 11.65 12.10 12.50 v 12out current limit 12out forced to 11v, v dd = 13v 150 ma quiescent v dd current v dd = 18v, run mode, no 12out load 50 100 ? internal regulator and reference v l output voltage shdn = v+, run/on3 = time/on5 = 0, 5.4v < v+ < 30v, 0ma < i load < 50ma 4.7 5.1 v v l undervoltage-lockout fault threshold falling edge, hysteresis = 1% 3.5 3.6 3.7 v v l switchover threshold rising edge of csl5, hysteresis = 1% 4.2 4.5 4.7 v ref output voltage no external load (note 4) 2.45 2.5 2.55 v 0 < i load < 50? 12.5 ref load regulation 0 < i load < 5ma 100.0 mv ref sink current 10 ? ref fault-lockout voltage falling edge 1.8 2.4 v v+ operating supply current v l switched over to csl5, 5v smps on 5 50 a v+ standby supply current v+ = 5.5v to 30v, both smpss off, includes current into shdn 30 60 ? v+ standby supply current in dropout v+ = 4.2v to 5.5v, both smpss off, includes current into shdn 50 200 ? v+ shutdown supply current v+ = 4.0v to 30v, shdn = 0 4 10 ? max8742 2.5 4 quiescent power consumption both smpss enabled, fb3 = fb5 = 0, csl3 = csh3 = 3.5v, csl5 = csh5 = 5.3v MAX8741 1.5 4 mw
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, both pwms on, sync = v l , v l load = 0, ref load = 0, skip = 0, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units fault detection overvoltage trip threshold with respect to unloaded output voltage 4 7 10 % overvoltage fault propagation delay csl_ driven 2% above overvoltage trip threshold 1.5 ? output undervoltage threshold with respect to unloaded output voltage 60 70 80 % output undervoltage-lockout time from each smps enabled, with respect to f osc 3300 4096 4700 clks thermal-shutdown threshold typical hysteresis = 10? +150 ? reset reset trip threshold with respect to unloaded output voltage, falling edge; typical hysteresis = 1% -7 -5.5 -4 % reset propagation delay falling edge, csl_ driven 2% below reset trip threshold 1.5 ? reset delay time with respect to f osc 27,000 32,000 37,000 clks inputs and outputs feedback-input leakage current fb3, fb5; secfb = 2.6v 1 50 na logic input-low voltage run/on3, skip , time/on5 (seq = ref), shdn , steer, sync 0.6 v logic input-high voltage run/on3, skip , time/on5 (seq = ref), shdn , steer, sync 2.4 v input leakage current run/on3, skip , time/on5 (seq = ref), shdn , steer, sync, seq; v pin = 0v or 3.3v 1a logic output-low voltage reset , i sink = 4ma 0.4 v logic output-high current reset = 3.5v 1 ma time/on5 input trip level seq = 0 or v l 2.4 2.6 v time/on5 source current time/on5 = 0, seq = 0 or v l 2.5 3 3.5 ? time/on5 on-resistance time/on5; run/on3 = 0, seq = 0 or v l 15 80 ? gate-driver sink/source current dl3, dh3, dl5, dh5; forced to 2v 1 a ssop package 1.5 7 gate-driver on-resistance high or low (note 5) qfn package 1.5 8 ?
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown _______________________________________________________________________________________ 5 electrical characteristics (v+ = 15v, both pwms on, sync = v l , v l load = 0, ref load = 0, skip = 0, t a = -40? to +85? , unless otherwise noted.) (note 6) parameter conditions min typ max units main smps controllers input voltage range 4.2 30.0 v 3v output voltage in adjustable mode v+ = 4.2v to 30v, csh3 - csl3 = 0, csl3 connected to fb3 2.42 2.58 v 3v output voltage in fixed mode v+ = 4.2v to 30v, 0 < csh3 - csl3 < 80mv, fb3 = 0 3.20 3.47 v 5v output voltage in adjustable mode v+ = 4.2v to 30v, csh5 - csl5 = 0, csl5 connected to fb5 2.42 2.58 v 5v output voltage in fixed mode v+ = 5.3v to 30v, 0 < csh5 - csl5 < 80mv, fb5 = 0 4.85 5.25 v output voltage adjust range either smps ref 5.5 v adjustable-mode threshold voltage dual-mode comparator 0.5 1.1 v csh3 - csl3 or csh5 - csl5 80 120 current-limit threshold skip = v l or v dd < 13v or secfb < 2.44v -50 -150 mv sync = v l 450 550 oscillator frequency sync = 0 283 383 khz sync = v l 95 maximum duty factor sync = 0 (note 2) 97 % sync input frequency range 400 583 khz flyback controller v dd regulation threshold falling edge (max8742) 13 14 v secfb regulation threshold falling edge (MAX8741) 2.44 2.60 v v dd shunt threshold rising edge, hysteresis = 1% (max8742) 18 20 v v dd shunt sink current v dd = 20v (max8742) 10 ma 12v linear regulator (max8742) 12out output voltage 13v < v dd < 18v, 0ma < i load < 100ma 11.65 12.50 v quiescent v dd current v dd = 18v, run mode, no 12out load 100 ? internal regulator and reference v l output voltage shdn = v+, run/on3 = time/on5 = 0, 5.4v < v+ < 30v, 0 < i load < 50ma 4.7 5.1 v v l undervoltage-lockout fault threshold falling edge, hysteresis = 1% 3.5 3.7 v v l switchover threshold rising edge of csl5, hysteresis = 1% 4.2 4.7 v ref output voltage no external load (note 4) 2.45 2.55 v 0 < i load < 50? 12.5 ref load regulation 0 < i load < 5ma 100.0 mv ref sink current 10 ? ref fault-lockout voltage falling edge 1.8 2.4 v v+ operating supply current v l switched over to csl5, 5v smps on 50 ?
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 6 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, both pwms on, sync = v l , v l load = 0, ref load = 0, skip = 0, t a = -40? to +85? , unless otherwise noted.) (note 6) parameter conditions min typ max units v+ standby supply current v+ = 5.5v to 30v, both smpss off, includes current into shdn 60 ? v+ standby supply current in dropout v+ = 4.2v to 5.5v, both smpss off, includes current into shdn 200 ? v+ shutdown supply current v+ = 4.0v to 30v, shdn = 0 10 a max8742 4 quiescent power consumption both smpss enabled, fb3 = fb5 = 0, csl3 = csh3 = 3.5v, csl5 = csh5 = 5.3v MAX8741 4 mw fault detection overvoltage trip threshold with respect to unloaded output voltage 4 10 % output undervoltage threshold with respect to unloaded output voltage 60 80 % output undervoltage-lockout time from each smps enabled, with respect to f osc 3300 4700 clks reset reset trip threshold with respect to unloaded output voltage, falling edge; typical hysteresis = 1% -7 -4 % reset delay time with respect to f osc 27,000 37,000 clks inputs and outputs feedback-input leakage current fb3, fb5; secfb = 2.6v 50 na logic input-low voltage run/on3, skip , time/on5 (seq = ref), shdn , steer, sync 0.6 v logic input-high voltage run/on3, skip , time/on5 (seq = ref), shdn , steer, sync 2.4 v logic output-low voltage reset , i sink = 4ma 0.4 v logic output-high current reset = 3.5v 1 ma time/on5 input trip level seq = 0 or v l 2.4 2.6 v time/on5 source current time/on5 = 0, seq = 0 or v l 2.5 3.5 ? time/on5 on-resistance time/on5; run/on3 = 0, seq = 0 or v l 80 ? ssop package 7 gate-driver on-resistance high or low (note 5) qfn package 8 ? note 1: each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mv increments. note 2: high duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating frequency (see the dropout operation section). note 3: off mode for the max8742 12v linear regulator occurs when the smps that has flyback feedback (v dd ) steered to it is disabled. in situations where the main outputs are being held up by external keep-alive supplies, turning off the 12out regulator prevent s a leakage path from the output-referred flyback winding, through the rectifier, and into v dd . note 4: since the reference uses v l as its supply, the reference? v+ line-regulation error is insignificant. note 5: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin qfn package. the ssop and thin qfn packages contain the same die, and the thin qfn package imposes no additional resistance in circuit. note 6: specifications from 0c to -40? are guaranteed by design, not production tested.
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown _______________________________________________________________________________________ 7 100 50 0.001 0.01 0.1 1 10 efficiency vs. 5v output current 60 MAX8741/42 toc01 5v output current (a) efficiency (%) 70 80 90 85 75 65 55 95 on5 = 5v on3 = 0v f = 500khz MAX8741 v+ = 15v v+ = 6v 100 50 0.001 0.01 0.1 1 10 efficiency vs. 3.3v output current 60 MAX8741/42 toc02 3.3v output current (a) efficiency (%) 70 80 90 85 75 65 55 95 on5 = on3 = 5v f = 500khz MAX8741 v+ = 15v v+ = 6v 800 600 400 200 0 010 51520 maximum v dd output current vs. input voltage MAX8741/42 toc03 input voltage (v) maximum v dd output current (ma) 5v load = 0 5v load = 3a 100 0.01 010 52030 no-load input current vs. input voltage 0.1 1 10 MAX8741/42 toc04 input voltage (v) input current (ma) 15 25 skip = 0v skip = v l on5 = on3 = 5v no load 10,000 1 010 52030 v+ standby input current vs. input voltage 10 100 1000 MAX8741/42 toc05 input voltage (v) input current ( a) 15 25 on5 = on3 = 0v no load 0 2 6 4 8 10 010 515202 530 shutdown input current vs. input voltage MAX8741/42 toc06 input voltage (v) input current ( a) shdn = 0v 0.001 0.01 1 minimum v in to v out differential vs. 5v output current MAX8741/42 toc07 5v output current (a) minimum v in to v out differential (mv) 1000 10 100 0.1 10 f = 500khz f = 333khz v out > 4.8v 1000 0.1 0.001 0.01 1 10 switching frequency vs. load current 1 10 100 MAX8741/42 toc08 load current (a) switching frequency (khz) 0.1 3.3v, v in = 15v 5v, v in = 15v 3.3v, v in = 6.5v 5v, v in = 6.5v 4.90 4.92 4.96 4.94 4.98 5.00 020 10 30 40 50 v l regulator output voltage vs. output current MAX8741/42 toc09 output current (ma) v l output voltage (v) v in = 15v on3 = on5 = 0v t ypical operating characteristics (circuit of figure 1, table 1, 6a/500khz components, t a = +25?, unless otherwise noted.)
5v load-transient response MAX8741/42 toc11 10v 0 5a 0 i lx5 5a/div v lx5 10v/div 5v output 5omv/div ac-coupled 20 s/div v in = 8v, i out = 1a to 5a 3.3v load-transient response MAX8741/42 toc12 10v 0 5a 0 i lx3 5a/div v lx3 10v/div 3.3v output 5omv/div ac-coupled 20 s/div v in = 8v, i out = 1a to 5a shutdown waveforms MAX8741/42 toc14 5v 3.3v 0 0 0 5v output 2v/div 3.3v output 2v/div dl3 5v/div dl5 5v/div shdn 5v/div 500 s/div r load3 = 5 ? , r load5 = 5 ? startup waveforms MAX8741/42 toc13 0 0 0 0 3.3v output 2v/div 5v output 5v/div time 2v/div run 5v/div 2ms/div seq = v l , o.o1 f capacitor on-time MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 1, table 1, 6a/500khz components, t a = +25?, unless otherwise noted.) 2.505 2.500 2.495 2.490 2.485 03 12 456 ref output voltage vs. output current MAX8741/42 toc10 output current (ma) ref output voltage (v) v in = 15v on3 = on5 = 0
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown _______________________________________________________________________________________ 9 pin description pin ssop tqfn name function 12 9 csh3 current-sense input for the 3.3v smps. current-limit level is 100mv referred to csl3. 23 0 csl3 current-sense input. also serves as the feedback input in fixed-output mode. 331 fb3 feedback input for the 3.3v smps. regulates at fb3 = ref (approximately 2.5v) in adjustable mode. fb3 is a dual-mode input that also selects the 3.3v fixed output- voltage setting when connected to gnd. connect fb3 to a resistor-divider for adjustable-output mode. 12out (max8742) 12v/120ma linear-regulator output. input supply comes from v dd . bypass 12out to gnd with 1? (min). 41 steer (MAX8741) logic-control input for secondary feedback. selects the pwm that uses a transformer and secondary feedback signal (secfb): steer = gnd: 3.3v smps uses transformer steer = v l : 5v smps uses transformer v dd (max8742) supply voltage input for the 12out linear regulator. also connects to an internal resistor-divider for secondary winding feedback and to an 18v overvoltage shunt regulator clamp. 52 secfb (MAX8741) secondary winding feedback input. normally connected to a resistor-divider from an auxiliary output. secfb regulates at v secfb = 2.5v (see the secondary feedback regulation loop section). connect to v l if not used. 63 sync oscillator synchronization and frequency select. connect to v l for 500khz operation; connect to gnd for 333khz operation. can be driven at 400khz to 583khz for external synchronization. 74 time/on5 dual-purpose timing capacitor pin and on/ off control input. see the power-up sequencing and on/ off controls section. 85 gnd low-noise analog ground and feedback reference point 97 ref 2.5v reference voltage output. bypass to gnd with 1? (min). 10 8 skip log i c- c ontr ol inp ut that d i sab l es id l e m od e w hen h i g h. c onnect to g n d for nor m al use. 11 9 reset active-low timed reset output. reset swings gnd to v l . goes high after a fixed 32,000 clock-cycle delay following power-up. 12 10 fb5 feedback input for the 5v smps. regulates at fb5 = ref (approximately 2.5v) in adjustable mode. fb5 is a dual-mode input that also selects the 5v fixed output- voltage setting when connected to gnd. connect fb5 to a resistor-divider for adjustable-output mode. 13 11 csl5 c ur r ent- s ense inp ut for the 5v s m p s . al so ser ves as the feed b ack i np ut i n fi xed - outp ut m od e, and as the b ootstr ap sup p l y i np ut w h en the vol tag e on c s l5/v l i s > 4.5v . 14 12 csh5 current-sense input for the 5v smps. current-limit level is 100mv referred to csl5.
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 10 ______________________________________________________________________________________ pin description (continued) pin ssop tqfn name function 15 13 seq pin-strap input that selects the smps power-up sequence: seq = gnd: 5v before 3.3v, reset output determined by both outputs seq = ref: separate on3/on5 controls, reset output determined by 3.3v output seq = v l : 3.3v before 5v, reset output determined by both outputs 16 14 dh5 gate-drive output for the 5v, high-side n-channel switch. dh5 is a floating driver output that swings from lx5 to bst5, riding on the lx5 switching-node voltage. 17 15 lx5 switching-node (inductor) connection. can swing 2v below ground without hazard. 18 17 bst5 boost capacitor connection for high-side gate drive (0.1?) 19 18 dl5 gate-drive output for the low-side synchronous-rectifier mosfet. swings 0 to v l . 20 19 pgnd power ground 21 20 v l 5v internal linear-regulator output. v l is also the supply-voltage rail for the chip. after the 5v smps output has reached 4.5v (typ), v l automatically switches to the output voltage through csl5 for bootstrapping. bypass to gnd with 4.7?. v l supplies up to 25ma for external loads. 22 21 v+ battery voltage input, 4.2v to 30v. bypass v+ to pgnd close to the ic with a 0.22? capacitor. connects to a linear regulator that powers v l . 23 22 shdn shutdown control input, active low. logic threshold is set at approximately 1v. for automatic startup, connect shdn to v+ through a 220k ? resistor and bypass shdn to gnd with a 0.01? capacitor. 24 23 dl3 gate-drive output for the low-side synchronous-rectifier mosfet. swings 0 to v l . 25 24 bst3 boost capacitor connection for high-side gate drive (0.1?) 26 26 lx3 switching-node (inductor) connection. can swing 2v below ground without hazard. 27 27 dh3 gate-drive output for the 3.3v, high-side n-channel switch. dh3 is a floating driver output that swings from lx3 to bst3, riding on the lx3 switching-node voltage. 28 28 run/on3 on/ off control input. see the power-up sequencing and on/ off controls section. 6, 16, 25, 32 n.c. no connection
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 11 MAX8741 v+ shdn v l secfb input on/off c3 7v to 24v ref seq 1 f 2.5v always on 5v always on q1 5v on/off 3.3v on/off q4 0.1 f 0.1 f l2 r2 3.3v output c2 4.7 f 0.1 f 4.7 f 0.1 f 10 ? c4 0.1 f q3 c5 0.1 f dl3 csh3 csl3 fb3 reset reset output skip steer q2 l1 r1 5v output c1 dl5 lx5 dh5 bst5 bst3 sync dh3 lx3 pgnd csl5 csh5 run/on3 time/on5 fb5 gnd figure 1. standard 3.3v/5v application circuit (MAX8741)
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 12 ______________________________________________________________________________________ standard application circuit the basic MAX8741 dual-output 3.3v/5v buck converter (figure 1) is easily adapted to meet a wide range of applications with inputs up to 28v by substituting com- ponents from table 1. these circuits represent a good set of tradeoffs between cost, size, and efficiency, while staying within the worst-case specification limits for stress-related parameters, such as capacitor ripple current. do not change the frequency of these circuits without first recalculating component values (particularly inductance value at maximum battery voltage). adding a schottky rectifier across each synchronous rectifier improves the efficiency of these circuits by approxi- mately 1%, but this rectifier is otherwise not needed because the mosfets required for these circuits typi- cally incorporate a high-speed silicon diode from drain to source. use a schottky rectifier rated at a dc current equal to at least one-third of the load current. detailed description the MAX8741/max8742 are dual, bicmos, switch- mode power-supply controllers designed primarily for buck-topology regulators in battery-powered applica- tions where high-efficiency and low-quiescent supply current are critical. light-load efficiency is enhanced by automatic idle-mode operation, a variable-frequency pulse-skipping mode that reduces transition and gate- charge losses. each step-down, power-switching cir- cuit consists of two n-channel mosfets, a rectifier, and an lc output filter. the output voltage is the aver- age ac voltage at the switching node, which is regulat- ed by changing the duty cycle of the mosfet switches. the gate-drive signal to the n-channel high- side mosfet must exceed the battery voltage, and is provided by a flying-capacitor boost circuit that uses a 100nf capacitor connected to bst_. table 1. component selection for standard 3.3v/5v application load current component 4a/333khz 4a/500khz 6a/500khz input range 7v to 24v 7v to 24v 7v to 24v frequency 333khz 500khz 500khz q1, q3 high-side mosfets 1/2 fairchild fds6982s or 1/2 international rectifier irf7901d1 1/2 fairchild fds6982s or 1/2 international rectifier irf7901d1 fairchild fds6612a or international rectifier irf7807v q2, q4 low-side mosfets with integrated schottky diodes 1/2 fairchild fds6982s or 1/2 international rectifier irf7901d1 1/2 fairchild fds6982s or 1/2 international rectifier irf7901d1 fairchild fds6670s or international rectifier irf7807dv1 c3 input capacitor 3 x 10?, 25v ceramic taiyo yuden tmk432bj106km 3 x 10?, 25v ceramic taiyo yuden tmk432bj106km 4 x 10?, 25v ceramic taiyo yuden tmk432bj106km c1 output capacitor 150?, 6v poscap sanyo 6tpc150m 150?, 6v poscap sanyo 6tpc150m 2 x 150?, 6v poscap sanyo 6tpc150m c2 output capacitor 2 x 150?, 4v poscap sanyo 4tpc150m 2 x 150?, 4v poscap sanyo 4tpc150m 2 x 220?, 4v poscap sanyo 4tpc220m r1, r2 resistors 0.018 ? dale wsl2512-r018-f 0.018 ? dale wsl2512-r018-f 0.012 ? dale wsl2512-r012-f l1 inductor 10?, 4.5a ferrite sumida cdrh124-100 7.0?, 5.2a ferrite sumida cei122-h-7r0 4.2?, 6.9a ferrite sumida cei122-h-4r2 l2 inductor 7.0?, 5.2a ferrite sumida cei122-h-7r0 5.6?, 5.2a ferrite sumida cei122-h-5r6 4.2?, 6.9a ferrite sumida cei122-h-4r2
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 13 the MAX8741/max8742 contain 10 major circuit blocks (figure 2). the two pulse-width-modulation (pwm) controllers each consist of a dual-mode feedback network and multiplexer, a multi-input pwm comparator, high-side and low-side gate drivers, and logic. the MAX8741/ max8742 contain fault-protection circuits that monitor the main pwm outputs for undervoltage and overvolt- age. a power-on sequence block controls the power- up timing of the main pwms and determines whether one or both of the outputs are monitored for undervoltage faults. the max8742 includes a secondary feedback net- work and 12v linear regulator to generate a 12v output from a coupled-inductor flyback winding. the MAX8741 has a secondary feedback input (secfb) instead, which allows a quasi-regulated, adjustable output, coupled- inductor flyback winding to be attached to either the 3.3v or the 5v main inductor. bias generator blocks include the 5v ic internal rail (v l ) linear regulator, 2.5v precision reference, and automatic bootstrap switchover circuit. the pwms share a common 333khz/500khz synchroniz- able oscillator. these internal ic blocks are not powered directly from the battery. instead, the 5v v l linear regulator steps down the battery voltage to supply both v l and the gate drivers. the synchronous-switch gate drivers are directly powered from v l , while the high-side switch gate drivers are indirectly powered from v l by an exter- nal diode-capacitor boost circuit. an automatic boot- strap circuit turns off the 5v linear regulator and powers the ic from the 5v pwm output voltage if the output is above 4.5v. pwm controller block the two pwm controllers are nearly identical. the only differences are fixed output settings (3.3v vs. 5v), the v l /csl5 bootstrap switch connected to the 5v pwm, and secfb. the heart of each current-mode pwm con- troller is a multi-input, open-loop comparator that sums three signals: the output-voltage error signal with respect to the reference voltage, the current-sense sig- nal, and the slope-compensation ramp (figure 3). the pwm controller is a direct-summing type, lacking a tra- ditional error amplifier and the phase shift associated with it. this direct-summing configuration approaches ideal cycle-by-cycle control over the output voltage. when skip = low, idle-mode circuitry automatically optimizes efficiency throughout the load current range. idle mode dramatically improves light-load efficiency by reducing the effective frequency, which reduces switching losses. it keeps the peak inductor current above 25% of the full current limit in an active cycle, allowing subsequent cycles to be skipped. idle mode transitions seamlessly to fixed-frequency pwm opera- tion as load current increases. with skip = high, the controller always operates in fixed- frequency pwm mode for lowest noise. each pulse from the oscillator sets the main pwm latch that turns on the high-side switch for a period determined by the duty fac- tor (approximately v out / v in ). as the high-side switch turns off, the synchronous-rectifier latch sets; 60ns later, the low-side switch turns on. the low-side switch stays on until the beginning of the next clock cycle. in pwm mode, the controller operates as a fixed-fre- quency current-mode controller where the duty ratio is set by the input/output voltage ratio. the current-mode feedback system regulates the peak inductor-current value as a function of the output-voltage error signal. in continuous-conduction mode, the average inductor current is nearly the same as the peak current, so the circuit acts as a switch-mode transconductance ampli- fier. this pushes the second output lc filter pole, nor- mally found in a duty-factor-controlled (voltage-mode) pwm, to a higher frequency. to preserve inner-loop stability and eliminate regenerative inductor current ?taircasing,?a slope-compensation ramp is summed into the main pwm comparator to make the apparent duty factor less than 50%. the MAX8741/max8742 use a relatively low loop gain, allowing the use of lower-cost output capacitors. the relative gains of the voltage-sense and current-sense inputs are weighted by the values of current sources that bias three differential input stages in the main pwm comparator (figure 4). the relative gain of the voltage comparator to the current comparator is internally fixed at k = 2:1. the low loop gain results in the 2% typical load-regulation error. the low value of loop gain helps reduce output-filter-capacitor size and cost by shifting the unity-gain crossover frequency to a lower level. table 2. component suppliers manufacturer website dale-vishay www.vishay.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com sanyo www.sanyo.com sumida www.sumida.com taiyo yuden www.t-yuden.com
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 14 ______________________________________________________________________________________ lpf 50khz ref 1.75v 2.388v r3 r4 - + + - 4.5v ref 2.5v ref 333khz to 500khz osc 5v pwm logic 5v linear reg v l bst3 dh3 lx3 dl3 3.3v v l on/off input 7v to 24v 5v always on csl5 shdn v+ sync 12v linear reg 12v 13v bst5 raw 15v dh5 dl5 v l pgnd csh5 csl5 csh3 csl3 fb5 reset seq 2.6v 1v 0.6v 0.6v v l gnd run/on3 time/on5 ref lx5 5v 12out v dd in secfb 3.3v pwm logic ref outputs up - + - + + - - + - + + - + - lpf 50khz timer power-on sequence logic r1 r2 fb3 - + + - max8742 ov/uv fault 2.68v figure 2. max8742 functional diagram
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 15 shoot- through control r q 30mv r q level shift 0.75 s single-shot 1x main pwm comparator osc level shift current limit synchronous- rectifier control ref shdn ck -100mv csh_ csl_ from feedback divider bst_ dh_ lx_ v l dl_ pgnd s s slope comp skip ref secfb counter dac soft-start figure 3. pwm controller functional diagram
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 16 ______________________________________________________________________________________ the output filter capacitors (figure 1, c1 and c2) set a dominant pole in the feedback loop that must roll off the loop gain to unity before encountering the zero intro- duced by the output capacitor? parasitic resistance (esr) (see the design procedure section). a 50khz pole-zero cancellation filter provides additional rolloff above the unity-gain crossover. this internal 50khz lowpass compensation filter cancels the zero due to fil- ter-capacitor esr. the 50khz filter is included in the loop in both fixed-output and adjustable-output modes. synchronous rectifier driver (dl) synchronous rectification reduces conduction losses in the rectifier by shunting the normal schottky catch diode with a low-resistance mosfet switch. also, the synchronous rectifier ensures proper startup of the boost gate-driver circuit. if the circuit is operating in continuous-conduction mode, the dl drive waveform is the complement of the dh high-side drive waveform (with controlled dead time to prevent cross-conduction or ?hoot- through?. in dis- continuous (light-load) mode, the synchronous switch is turned off as the inductor current falls through zero. the synchronous rectifier works under all operating condi- tions, including idle mode. the secfb signal further controls the synchronous switch timing in order to improve multiple-output cross-regulation (see the secondary feedback regulation loop section). internal v l and ref supplies an internal regulator produces the 5v supply (v l ) that powers the pwm controller, logic, reference, and other blocks within the ic. this 5v low-dropout linear regula- tor supplies up to 25ma for external loads, with a reserve of 25ma for supplying gate-drive power. bypass v l to gnd with 4.7?. important: ensure that v l does not exceed 6v. measure v l with the main output fully loaded. if it is pumped above 5.5v, either excessive boost-diode capacitance or excessive ripple at v+ is the probable cause. use only small-signal diodes for the boost cir- cuit (10ma to 100ma schottky or 1n4148 are pre- ferred), and bypass v+ to pgnd with 4.7? directly at the package pins. table 3. skip pwm table skip load current mode description low light idle pulse skipping, supply current = 250? at v in =12v, discontinuous inductor low heavy pwm constant-frequency pwm continuous-inductor current high light pwm constant-frequency pwm continuous-inductor current high heavy pwm constant-frequency pwm continuous-inductor current fb_ ref csh_ csl_ slope compensation v l i1 r1 r2 to pwm logic output driver uncompensated high-speed level translator and buffer i2 i3 v bias figure 4. main pwm comparator block diagram
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 17 the 2.5v reference (ref) is accurate to ?% over tem- perature, making ref useful as a precision system ref- erence. bypass ref to gnd with 1f (min). ref can supply up to 5ma for external loads. (bypass ref with a minimum 1?/ma reference load current.) however, if extremely accurate specifications for both the main out- put voltages and ref are essential, avoid loading ref more than 100?. loading ref reduces the main out- put voltage slightly, because of the reference load- regulation error. when the 5v main output voltage is above 4.5v, an inter- nal p-channel mosfet switch connects csl5 to v l , while simultaneously shutting down the v l linear regula- tor. this action bootstraps the ic, powering the internal circuitry from the output voltage, rather than through a linear regulator from the battery. bootstrapping reduces power dissipation due to gate charge and quiescent losses by providing that power from a 90%-efficient switch-mode source, rather than from a much-less-effi- cient linear regulator. boost high-side gate-drive supply (bst3 and bst5) gate-drive voltage for the high-side n-channel switches is generated by a flying-capacitor boost circuit (figure 2). the capacitor between bst_ and lx_ is alternately charged from the v l supply and placed parallel to the high-side mosfet? gate-source terminals. on startup, the synchronous rectifier (low-side mosfet) forces lx_ to 0v and charges the boost capacitors to 5v. on the second half-cycle, the smps turns on the high-side mosfet by closing an internal switch bet ween bst_ and dh_. this provides the necessary enhancement voltage to turn on the high-side switch, an action that ?oosts?the 5v gate-drive signal above the battery voltage. ringing at the high-side mosfet gate (dh3 and dh5) in discontinuous-conduction mode (light loads) is a nat- ural operating condition. it is caused by residual ener- gy in the tank circuit, formed by the inductor and stray capacitance at the switching node, lx. the gate-drive negative rail is referred to lx, so any ringing there is directly coupled to the gate-drive output. current-limiting and current-sense inputs (csh and csl) the current-limit circuit resets the main pwm latch and turns off the high-side mosfet switch whenever the voltage difference between csh and csl exceeds 100mv. this limiting is effective for both current flow directions, putting the threshold limit at ?00mv. the tolerance on the positive current limit is ?0%, so the external low-value sense resistor (r1) must be sized for 80mv / i peak , where i peak is the required peak induc- tor current to support the full load current, while compo- nents must be designed to withstand continuous- current stresses of 120mv/r1. for breadboarding or for very-high-current applica- tions, it may be useful to wire the current-sense inputs with a twisted pair, rather than pc traces. (this twisted pair need not be special; two pieces of wire-wrap wire twisted together is sufficient.) this reduces the possible noise picked up at csh_ and csl_, which can cause unstable switching and reduced output current. the csl5 input also serves as the ic? bootstrap supply input. whenever v csl5 > 4.5v, an internal switch con- nects csl5 to v l . oscillator frequency and synchronization (sync) the sync input controls the oscillator frequency. low selects 333khz; high selects 500khz. sync can also be used to synchronize with an external 5v cmos or ttl clock generator. sync has a guaranteed 400khz to 583khz capture range. a high-to-low transition on sync initiates a new cycle. operating at 500khz optimizes the application circuit for component size and cost; 333khz operation provides increased efficiency, lower dropout, and improved load- transient response at low input-output voltage differ- ences (see the low-voltage operation section). shutdown mode holding shdn low puts the ic into its 4? shutdown mode. shdn is logic input with a threshold of about 1v (the v th of an internal n-channel mosfet). for automatic startup, bypass shdn to gnd with a 0.01? capacitor and connect it to v+ through a 220k ? resistor. power-up sequencing and on/ off controls startup is controlled by run/on3 and time/on5 in conjunction with seq. with seq connected to ref, the two control inputs act as separate on/ off controls for each supply. with seq connected to v l or gnd, run/on3 becomes the master on/ off control input and time/on5 becomes a timing pin, with the delay between the two supplies determined by an external capacitor. the delay is approximately 800?/nf. the 3.3v supply powers up first if seq is connected to v l , and the 5v supply is first if seq is connected to gnd. when driving time/on5 as a control input with external logic, always place a resistor (>1k ? ) in series with the input. this prevents possible crowbar current due to the internal discharge pulldown transistor, which turns on in standby mode and momentarily at the first power- up or in shutdown mode.
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 18 ______________________________________________________________________________________ dl_ is kept low whenever the corresponding smps is disabled, and in shutdown. since the outputs are not actively discharged by the smps controller, the negative output voltage caused by quickly discharging the output through the inductor and low-side mosfet is eliminated. the output voltage discharges at a rate determined only by the output capacitance and load current. reset power-good voltage monitor the power-good monitor generates a system reset signal. at first power-up, reset is held low until both the 3.3v and 5v smps outputs are in regulation. at this point, an internal timer begins counting oscillator puls- es, and reset continues to be held low until 32,000 cycles have elapsed. after this timeout period (64ms at 500khz or 96ms at 333khz), reset is actively pulled up to v l . if seq is connected to ref (for separate on3/on5 controls), only the 3.3v smps is monitored the 5v smps is ignored. output undervoltage shutdown protection the output undervoltage-lockout circuit is similar to foldback current limiting, but employs a timer rather than a variable current limit. each smps has an under- voltage protection circuit that is activated 4096 clock cycles after the smps is enabled. if either smps output is under 70% of the nominal value, both smpss are latched off with dh_ and dl_ driven low. they won? restart until shdn or run/on3 is toggled, or until v+ power is cycled below 1v. output overvoltage protection both smps outputs are monitored for overvoltage. if either output is more than 7% above the nominal regu- lation point, both smps outputs are latched off and the low-side gate driver (dl_) of the faulted side is latched high. the smps does not restart until shdn is brought low and v l falls below its 2v (typ) por level. to ensure overvoltage protection on initial power-up, connect signal diodes from both output voltages to v l (cathodes to v l ) to eliminate the v l power-up delay. this circuitry protects the load from accidental overvolt- age caused by a short circuit across the high-side power mosfets. this scheme relies on the presence of a fuse, in series with the battery, which is blown by the resulting crowbar current. low-noise operation (pwm mode) pwm mode ( skip = high) minimizes rf and audio inter- ference in noise-sensitive applications (such as hi-fi multi- media-equipped systems), cellular phones, rf communicating computers, and electromagnetic pen entry systems. see the summary of operating modes in table 3. skip can be driven from an external logic signal. interference due to switching noise is reduced in pwm mode by ensuring a constant switching frequency, thus concentrating the emissions at a known frequency out- side the system audio or if bands. choose an oscillator frequency for which switching frequency harmonics do not overlap a sensitive frequency band. if necessary, synchronize the oscillator to a tight-tolerance external clock generator. to extend the output-voltage regula- tion range, constant operating frequency is not main- tained under overload or dropout conditions (see the dropout operation section). pwm mode ( skip = high) forces two changes upon the pwm controllers. first, it disables the minimum-current comparator, ensuring fixed-frequency operation. second, it changes the detection threshold for reverse current limit from 0 to -100mv, allowing the inductor table 4. operating modes shdn seq run/on3 time/on5 mode description low x x x shutdown all circuit blocks turned off. supply current = 4?. high ref low low standby both smpss off. supply current = 30?. high ref high low run 3.3v smps enabled/5v off. high ref low high run 5v smps enabled/3.3v off. high ref high high run both smpss enabled. high gnd low timing capacitor standby both smpss off. supply current = 30?. high gnd high timing capacitor run both smpss enabled. 5v enabled before 3.3v. high v l low timing capacitor standby both smpss off. supply current = 30?. high v l high timing capacitor run both smpss enabled. 3.3v enabled before 5v.
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 19 current to reverse at light loads. this results in fixed-fre- quency operation and continuous inductor-current flow. this eliminates discontinuous-mode inductor ringing and improves cross-regulation of transformer-coupled multiple-output supplies, particularly in circuits that do not use additional secondary regulation through secfb or v dd . in most applications, connect skip to gnd to minimize quiescent supply current. v l supply current with skip high is typically 30ma, depending on external mosfet gate capacitance and switching losses. internal digital soft-start circuit soft-start allows a gradual increase of the internal cur- rent-limit level at startup to reduce input surge currents. both smpss contain internal digital soft-start circuits, each controlled by a counter, a digital-to-analog con- verter (dac), and a current-limit comparator. in shut- down or standby mode, the soft-start counter is reset to zero. when an smps is enabled, its counter starts counting oscillator pulses, and the dac begins incre- menting the comparison voltage applied to the current- limit comparator. the dac output increases from 0 to 100mv in five equal steps as the count increases to 512 clocks. as a result, the main output capacitor charges up relatively slowly. the exact time of the out- put rise depends on output capacitance and load cur- rent, and is typically 600? with a 500khz oscillator. dropout operation dropout (low input-output differential operation) is enhanced by stretching the clock pulse width to increase the maximum duty factor. the algorithm fol- lows: if the output voltage (v out ) drops out of regula- tion without the current limit having been reached, the smps skips an off-time period (extending the on-time). at the end of the cycle, if the output is still out of regula- tion, the smps skips another off-time period. this action can continue until three off-time periods are skipped, effectively dividing the clock frequency by as much as four. the typical pwm minimum off-time is 300ns, regardless of the operating frequency. lowering the operating fre- quency raises the maximum duty factor above 97%. adjustable-output feedback (dual-mode fb) fixed, preset output voltages are selected when fb_ is connected to ground. adjusting the main output volt- age with external resistors is simple for any of the MAX8741/max8742, through resistor-dividers connect- ed to fb3 and fb5 (figure 2). calculate the output volt- age with the following formula: v out = v ref (1 + r1 / r2) where v ref = 2.5v nominal. the nominal output should be set approximately 1% or 2% high to make up for the MAX8741/max8742 -2% typ- ical load-regulation error. for example, if designing for a 3.0v output, use a resistor ratio that results in a nominal output voltage of 3.05v. this slight offsetting gives the best possible accuracy. recommended normal values for r2 range from 5k ? to 100k ? . to achieve a 2.5v nom- inal output, connect fb_ directly to csl_. remote output-voltage sensing, while not possible in fixed-output mode due to the combined nature of the voltage-sense and current-sense inputs (csl3 and csl5), is easy to do in adjustable mode by using the top of the external resistor-divider as the remote sense point. when using adjustable mode, it is a good idea to always set the ?.3v output?to a lower voltage than the ?v output.?the 3.3v output must always be less than v l , so that the voltage on csh3 and csl3 is within the common-mode range of the current-sense inputs. while v l is nominally 5v, it can be as low as 4.7v when linear- ly regulating, and as low as 4.2v when automatically bootstrapped to csh5. secondary feedback regulation loop (secfb or v dd ) a flyback-winding control loop regulates a secondary winding output, improving cross-regulation when the primary output is lightly loaded or when there is a low input-output differential voltage. if v dd or secfb falls below its regulation threshold, the low-side switch is turned on for an extra 0.75?. this reverses the induc- tor (primary) current, pulling current from the output fil- ter capacitor and causing the flyback transformer to operate in forward mode. the low impedance present- ed by the transformer secondary in forward mode dumps current into the secondary output, charging up the secondary capacitor and bringing v dd or secfb back into regulation. the secondary feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavi- ly loaded. in this condition, secondary output accuracy is determined by the secondary rectifier drop, trans- former turns ratio, and accuracy of the main output
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 20 ______________________________________________________________________________________ voltage. a linear postregulator may still be needed to meet strict output-accuracy specifications. the max8742 has a v dd pin that regulates at a fixed 13.5v, set by an internal resistor-divider. the MAX8741 has an adjustable secondary-output voltage set by an external resistor-divider on secfb (figure 5). ordinarily, the secondary regulation point is set 5% to 10% below the voltage normally produced by the flyback effect. for example, if the output voltage as determined by turns ratio is 15v, set the feedback resistor ratio to produce 13.5v. otherwise, the secfb one-shot might be triggered unintentionally, unnecessarily increasing supply current and output noise. 12v linear-regulator output (max8742) the max8742 includes a 12v linear-regulator output capable of delivering 120ma of output current. typically, greater current is available at the expense of output accuracy. if an accurate output of more than 120ma is needed, an external pass transistor can be added. the circuit in figure 6 delivers more than 200ma. total output current is constrained by the v+ input voltage and the transformer primary load (see the maximum v dd output current vs. input voltage graphs in the typical operating characteristics ). design procedure the three predesigned 3v/5v standard application cir- cuits (figure 1 and table 1) contain ready-to-use solu- tions for common application needs. also, one standard flyback transformer circuit supports the 12out linear regulator in the applications information section. use the following design procedure to optimize these basic schematics for different voltage or current requirements. before beginning a design, however, firmly establish the following: ? aximum input (battery) voltage, v in(max) . this value should include the worst-case conditions, such as no-load operation when a battery charger or ac adapter is connected but no battery is installed. v in(max) must not exceed 30v. minimum input (battery) voltage, v in(min) .this should be taken at full load under the lowest battery conditions. if v in(min) is less than 4.2v, use an exter- nal circuit to externally hold v l above the v l undervolt- age- lockout threshold. if the minimum input-output difference is less than 1.5v, the filter capacitance required to maintain good ac load regulation increas- es (see the low-voltage operation section). MAX8741 positive secondary output main output dh_ v+ secfb 2.5v ref r2 r1 1-shot trig dl_ where v ref (nominal) = 2.5v +v trip = v ref ( 1 + ) r1 r2 max8742 v dd output 12v output 200ma main output 2n3906 0.1 f 0.1 f 0.1 f 2.2 f 10 f 10 ? v+ v dd 12out dh_ dl_ figure 5. adjusting the secondary output voltage with secfb figure 6. increased 12v linear-regulator output current
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 21 inductor value the exact inductor value is not critical and can be freely adjusted to make trade-offs between size, cost, and efficiency. lower inductor values minimize size and cost but reduce efficiency due to higher peak-cur- rent levels. the smallest inductor is achieved by lower- ing the inductance until the circuit operates at the border between continuous and discontinuous mode. further reducing the inductor value below this crossover point results in discontinuous-conduction operation even at full load. this helps lower output-filter capacitance requirements, but efficiency suffers due to high i 2 r losses. on the other hand, higher inductor val- ues mean greater efficiency, but resistive losses due to extra wire turns eventually exceed the benefit gained from lower peak-current levels. also, high inductor val- ues can affect load-transient response (see the v sag equation in the low-voltage operation section). the equations that follow are for continuous-conduction operation, since the MAX8741/max8742 are intended mainly for high-efficiency, battery-powered applica- tions. discontinuous conduction does not affect normal idle-mode operation. three key inductor parameters must be specified: induc- tance value (l), peak current (i peak ), and dc resistance (r d c ). the following equation includes a constant (lir), which is the ratio of inductor peak-to-peak ac current to dc load current. a higher lir value allows smaller inductance but results in higher losses and higher ripple. a good compromise between size and losses is found at a 30% ripple-current to load-current ratio (lir = 0.3), which corresponds to a peak-inductor current 1.15 times higher than the dc load current: where: f = switching frequency, normally 333khz or 500khz i out = maximum dc load current lir = ratio of ac to dc inductor current, typically 0.3; should be >0.15 the nominal peak-inductor current at full load is 1.15 ? i out if the above equation is used; otherwise, the peak current can be calculated by: the inductor? dc resistance should be low enough that r dc ? i peak < 100mv, as it is a key parameter for effi- ciency performance. if a standard off-the-shelf inductor is not available, choose a core with an li 2 rating greater than l ? i peak 2 and wind it with the largest diameter wire that fits the winding area. ferrite core material is strongly preferred. shielded-core geometries help keep noise, emi, and switching-waveform jitter low. current-sense resistor value the current-sense resistor value is calculated accord- ing to the worst-case low current-limit threshold voltage (from the electrical characteristics ) and the peak inductor current: use i peak from the second equation in the inductor value section. use the calculated value of r sense to size the mosfet switches and specify inductor saturation-current ratings according to the worst-case high current-limit threshold voltage: low-inductance resistors, such as surface-mount metal-film, are recommended. input-capacitor value the input filter capacitor is usually selected according to input ripple-current requirements and voltage rating, rather than capacitor value. ceramic capacitors or sanyo os-con capacitors are typically used to handle the power-up surge currents, especially when connect- ing to robust ac adapters or low-impedance batteries. rms input ripple current (i rms ) is determined by the input voltage and load current, with the worst case occurring at v in = 2 ? v out : therefore, when v in is 2 x v out : i i rms load = 2 ii vvv v rms load out in out in = () - i mv r peak max sense () = 120 r mv i sense peak = 80 ii vv v flv peak load out in max out in max =+ () () () () - 2 l vv v vfi lir out in max out in max out = () () () -
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 22 ______________________________________________________________________________________ bypassing v+ bypass the v+ input with a 4.7? tantalum capacitor paralleled with a 0.1? ceramic capacitor, close to the ic. a 10 ? series resistor to v in is also recommended. bypassing v l bypass the v l output with a 4.7? tantalum capacitor paralleled with a 0.1? ceramic capacitor, close to the device. output-filter capacitor value the output-filter capacitor values are generally deter- mined by the esr and voltage-rating requirements, rather than actual capacitance requirements for loop sta- bility. in other words, the low-esr electrolytic capacitor that meets the esr requirement usually has more output capacitance than is required for ac stability. use only specialized low-esr capacitors intended for switching- regulator applications, such as avx tps, sanyo poscap, or kemet t510. to ensure stability, the capaci- tor must meet both minimum capacitance and maximum esr values as given in the following equations: these equations are worst case, with 45 of phase mar- gin to ensure jitter-free, fixed-frequency operation and provide a nicely damped output response for zero to full-load step changes. some cost-conscious designers may wish to bend these rules with less-expensive capacitors, particularly if the load lacks large step changes. this practice is tolerable if some bench test- ing over temperature is done to verify acceptable noise and transient response. no well-defined boundary exists between stable and unstable operation. as phase margin is reduced, the first symptom is a bit of timing jitter, which shows up as blurred edges in the switching waveforms where the scope does not quite sync up. technically speaking, this jitter (usually harmless) is unstable operation, since the duty factor varies slightly. as capacitors with higher esrs are used, the jitter becomes more pronounced, and the load-transient output-voltage waveform starts looking ragged at the edges. eventually, the load-transient wave- form has enough ringing on it that the peak noise levels exceed the allowable output-voltage tolerance. note that even with zero phase margin and gross instability pre- sent, the output-voltage noise never gets much worse than i peak ? r esr (under constant loads). the output-voltage ripple is usually dominated by the filter capacitor? esr, and can be approximated as i ripple ? r esr . there is also a capacitive term, so the full equation for ripple in continuous-conduction mode is v noise(p-p) = i ripple ? [r esr + 1/(2 ? ? f ? c out )]. in idle mode, the inductor current becomes discontinuous, with high peaks and widely spaced pulses, so the noise can actually be higher at light load (compared to full load). in idle mode, calculate the out- put ripple as follows: transformer design (for auxiliary outputs only) buck-plus-flyback applications, sometimes called ?ou- pled-inductor?topologies, need a transformer to gener- ate multiple output voltages. performing the basic electrical design is a simple task of calculating turns ratios and adding the power delivered to the secondary to calculate the current-sense resistor and primary inductance. however, extremes of low input-output dif- ferentials, widely different output loading levels, and high turns ratios can complicate the design due to par- asitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage induc- tance. for examples of what is possible with real- world transformers, see the maximum v dd output current vs. input voltage graph in the typical operating characteristics . power from the main and secondary outputs is com- bined to get an equivalent current referred to the main output voltage (see the inductor value section for para- meter definitions). set the current-sense resistor value at 80mv / i total . p total = the sum of the output power from all outputs i total = p total / v out = the equivalent output current referred to v out l vv v vfi lir turns ratio n vv vvv primary out in max out in max total sec fwd out min rect sense = = + ++ () () () () - v r r lv vv rc noise p p esr sense out in out sense out () . .[//()] - - = + + 0 025 0 0003 1 1 2 c vvv vr f r rv v out ref out in min out sense esr sense out ref > + < (/) () 1
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 23 where: v sec = the minimum required rectified secondary out- put voltage v fwd = the forward drop across the secondary rectifier v out(min) = the minimum value of the main output volt- age (from the electrical characteristics tables) v rect = the on-state voltage drop across the synchronous-rectifier mosfet v sense = the voltage drop across the sense resistor in positive-output applications, the transformer sec- ondary return is often referred to the main output volt- age, rather than to ground, to reduce the needed turns ratio. in this case, the main output voltage must first be subtracted from the secondary voltage to obtain v sec . selecting other components mosfet switches the high-current n-channel mosfets must be logic- level types with guaranteed on-resistance specifica- tions at v gs = 4.5v. lower gate-threshold specifications are better (i.e., 2v max rather than 3v max). drain-source breakdown voltage ratings must at least equal the maximum input voltage, preferably with a 20% derating factor. the best mosfets have the lowest on-resistance per nanocoulomb of gate charge. multiplying r ds(on) ? q g provides a good figure for comparing various mosfets. newer mosfet process technologies with dense cell structures generally per- form best. the internal gate drivers tolerate >100nc total gate charge, but 70nc is a more practical upper limit to maintain best switching times. in high-current applications, mosfet package power dissipation often becomes a dominant design factor. i 2 r power losses are the greatest heat contributor for both high-side and low-side mosfets. i 2 r losses are distributed between q1 and q2 according to duty fac- tor (see the following equations). generally, switching losses affect only the upper mosfet, since the schottky rectifier clamps the switching node in most cases before the synchronous rectifier turns on. gate- charge losses are dissipated by the driver and do not heat the mosfet. calculate the temperature rise according to package thermal-resistance specifications to ensure that both mosfets are within their maximum junction temperature at high ambient temperature. the worst-case dissipation for the high-side mosfet occurs at both extremes of input voltage, and the worst-case dissipation for the low-side mosfet occurs at maximum input voltage: where: on-state voltage drop v q_ = i load ? r ds(on) c rss = mosfet reverse transfer capacitance i gate = dh driver peak output current capability (1a typ) 20ns = dh driver inherent rise/fall time during short circuit, the MAX8741/max8742s' output undervoltage shutdown protects the synchronous recti- fier under output short-circuit conditions. to reduce emi, add a 0.1? ceramic capacitor from the high-side switch drain to the low-side switch source. rectifier clamp diode the rectifier diode is a clamp across the low-side mosfet that catches the negative inductor swing dur- ing the 60ns dead time between turning one mosfet off and each low-side mosfet on. the latest genera- tions of mosfets incorporate a high-speed schottky diode, which serves as an adequate clamp diode. for mosfets without integrated schottky diodes, place a schottky diode in parallel with the low-side mosfet. use a schottky diode with a dc current rating equal to 1/3rd the load current. the schottky diode? rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% der- ating factor. boost-supply diode a signal diode such as a 1n4148 works well in most applications. if the input voltage can go below +6v, use a small (20ma) schottky diode for slightly improved efficiency and dropout characteristics. do not use large-power diodes, such as 1n5817 or 1n4001, since high junction capacitance can pump up v l to exces- sive voltages. pd i r duty vi f vc i ns pd i r duty duty v v v v upperfet load ds on in load in rss gate upperfet load ds on out q in q = + + ? ? ? ? ? ? = =+ ()() 2 2 21 20 1 () () () / - -
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 24 ______________________________________________________________________________________ rectifier diode (transformer secondary diode) the secondary diode in coupled-inductor applications must withstand flyback voltages greater than 60v, which usually rules out most schottky rectifiers. common silicon rectifiers, such as the 1n4001, are also prohibited because they are too slow. this often makes fast silicon rectifiers such as the murs120 the only choice. the flyback voltage across the rectifier is relat- ed to the v in - v out difference, according to the trans- former turns ratio: v flyback = v sec + (v in - v out ) ? n where: n = the transformer turns ratio sec/pri v sec = the maximum secondary dc output voltage v out = the primary (main) output voltage subtract the main output voltage (v out ) from v flyback in this equation if the secondary winding is returned to v out and not to ground. the diode reverse- breakdown rating must also accommodate any ringing due to leakage inductance. the rectifier diode? current rating should be at least twice the dc load current on the secondary output. low-voltage operation low input voltages and low input-output differential volt- ages each require extra care in their design. low absolute input voltages can cause the v l linear regulator to enter dropout and eventually shut itself off. low input voltages relative to the output (low v in - v out differential) can cause bad load regulation in multi-output flyback applications (see the design equations in the transformer design section). also, low v in - v out differentials can also cause the output voltage to sag when the load cur- rent changes abruptly. the amplitude of the sag is a function of inductor value and maximum duty factor (an electrical characteristics parameter, 97% guaranteed over temperature at f = 333khz), as follows: the cure for low-voltage sag is to increase the output capacitor? value. take a 333khz/6a application circuit as an example, at v in = +5.5v, v out = +5v, l = 6.7?, f = 333khz, i step = 3a (half-load step), a total capaci- tance of 470? keeps the sag less than 200mv. the capacitance is higher than that shown in the typical application circuit because of the lower input voltage. note that only the capacitance requirement increases and the esr requirements do not change. therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-esr capacitor. applications information heavy-load efficiency considerations the major efficiency-loss mechanisms under loads are, in the usual order of importance: p(i 2 r) = i 2 r losses p(tran) = transition losses p(gate) = gate-charge losses p(diode) = diode-conduction losses p(cap) = input capacitor esr losses p(ic) = losses due to the ic? operating supply current inductor core losses are fairly low at heavy loads because the inductor? ac current component is small. therefore, they are not accounted for in this analysis. ferrite cores are preferred, especially at 300khz, but powdered cores, such as kool-mu, can work well: efficiency = p out /p in ? 100% = p out /(p out + p total ) ? 100% p total = p(i 2 r) + p(tran) + p(gate) + p(diode) + p(cap) + p(ic) p (i 2 r) = i load 2 x (r dc + r ds(on) + r sense ) where r dc is the dc resistance of the coil, r ds(on) is the mosfet on-resistance, and r sense is the current- sense resistor value. the r ds(on) term assumes identi- cal mosfets for the high-side and low-side switches because they time-share the inductor current. if the mosfets are not identical, their losses can be estimat- ed by averaging the losses according to duty factor: where c rss is the reverse transfer capacitance of the high-side mosfet (a data sheet parameter), i gate is the dh gate-driver peak output current (1.5a typ), and 20ns is the rise/fall time of the dh driver (20ns typ): p(gate) = q g ? f ? v l where v l is the internal-logic-supply voltage (5v), and q g is the sum of the gate-charge values for low-side and high-side switches. for matched mosfets, q g is twice the data sheet value of an individual mosfet. if v out is set to less than 4.5v, replace v l in this equa- tion with v batt . in this case, efficiency can be p tran v i fvci ns in load in rss gate () / = () [] 3 2 20 - v il cv dv sag step out in min max out = 2 2( ) () -
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 25 improved by connecting v l to an efficient 5v source, such as the system 5v supply: p(diode) = i load ? v fwd ? t d ? f where t d is the diode-conduction time (120ns typ) and v fwd is the forward voltage of the diode. this power is dissipated in the mosfet body diode if no external schottky diode is used: p(cap) = (i rms ) 2 x r esr where i rms is the input ripple current as calculated in the design procedure and input-capacitor value sections. light-load efficiency considerations under light loads, the pwm operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. this makes the inductor current? ac component high compared to the load current, which increases core losses and i 2 r losses in the output filter capacitors. for best light-load efficien- cy, use mosfets with moderate gate-charge levels, and use ferrite, mpp, or other low-loss core material. lossless-inductor current sensing the dc resistance (dcr) of the inductor can be used to sense inductor current to improve the efficiency and to reduce the cost by eliminating the sense resistor. figure 7 shows the sense circuit, where l is the induc- tance, r l is the inductor dcr, and r s and c s form an rc lowpass sense network. if the time constant of the inductor is equal to that of the sense network, i.e.,: then the voltage across c s becomes: where i l is the inductor current. determine the required sense-resistor value using the equation given in the current-sense resistor value section. choose an inductor with dcr equal to or greater than the sense resistor value. if the dcr is greater than the sense-resistor value, use a divider to vri sll = l r rc l ss = symptom condition root cause solution sag or droop in v out under step-load change low v in - v out differential, <1.5v limited inductor-current slew rate per cycle. increase bulk output capacitance per formula (see the low-voltage operation section). reduce inductor value. dropout voltage is too high (v out follows v in as v in decreases) low v in - v out differential, <1v maximum duty-cycle limits exceeded. reduce operation to 333khz. reduce mosfet on-resistance and coil dcr. unstable?itters between different duty factors and frequencies low v in - v out differential, <0.5v normal function of internal low- dropout circuitry. increase the minimum input voltage or ignore. secondary output does not support a load low v in - v out differential, v in < 1.3 x v out(main) not enough duty cycle left to initiate forward-mode operation. small ac current in primary cannot store energy for flyback operation. reduce operation to 333khz. reduce secondary impedances; use a schottky diode, if possible. stack secondary winding on the main output. poor efficiency low input voltage, <5v v l linear regulator is going into dropout and is not providing good gate-drive levels. use a small 20ma schottky diode for boost diode. supply v l from an external source. does not start under load or quits before battery is completely dead low input voltage, <4.5v v l output is so low that it hits the v l uvlo threshold. supply v l from an external source other than v in , such as the system 5v supply. table 5. low-voltage troubleshooting chart
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 26 ______________________________________________________________________________________ scale down the voltage. use the maximum inductance and minimum dcr to get the maximum possible induc- tor time constant. select r s and c s so that the maxi- mum sense-network time constant is equal to or greater than the maximum inductor time constant. reduced output-capacitance application in applications where higher output ripple is accept- able, lower output capacitance or higher esr output capacitors can be used. in such cases, cycle-by-cycle stability is maintained by adding feed-forward compen- sation to offset for the increased output esr. figure 8 shows the addition of the feed-forward compensation circuit. c fb provides noise filtering, r ff is the feed-for- ward resistor, and c lx provides dc blocking. use 100pf for c fb and c lx . select r ff according to the equation below: set the value for r ff close to the calculation. do not make r ff too small as that introduces too much feed- forward, possibly causing an overvoltage to be seen at the feedback pin, and changing the mode of operation to a voltage mode. pc board layout considerations good pc board layout is required in order to achieve specified noise, efficiency, and stability performance. the pc board layout artist must be given explicit instructions, preferably a pencil sketch showing the placement of power-switching components and high- current routing. a ground plane is essential for optimum performance. in most applications, the circuit is located on a multilayer board, and full use of the four or more copper layers is recommended. use the top layer for high-current connections, the bottom layer for quiet connections (ref, ss, gnd), and the inner layers for an uninterrupted ground plane. use the following step- by-step guide: 1) place the high-power components (figure 1, c1, c3, c4, q1, q2, l1, and r1) first, with their grounds adjacent: priority 1: minimize current-sense resistor trace lengths and ensure accurate current sensing with kelvin connections (figure 9). priority 2: minimize ground trace lengths in the high-current paths (discussed below). priority 3: minimize other trace lengths in the high-current paths. a) use >5mm-wide traces b) cin to high-side mosfet drain: 10mm max length c) rectifier diode cathode to low-side mosfet: 5mm max length r rlf esr ff 43 l dl_ dh_ lx_ MAX8741 max8742 csh_ csl_ inductor r l v out v in c in c out c s r s figure 7. lossless inductor current sensing r3 r4 fb_ l c in dl_ dh_ lx_ MAX8741 max8742 csh_ csl_ v in c lx r ff c fb r sense v out c out figure 8. adding feed-forward compensation
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 27 d) lx node (mosfets, rectifier cathode, induc tor): 15mm max length ideally, surface-mount power components are butted up to one another with their ground terminals almost touch- ing. these high-current grounds are then connected to each other with a wide filled zone of top-layer copper so they do not go through vias. the resulting top layer ?ub- ground-plane?is connected to the normal inner-layer ground plane at the output ground terminals, which ensures that the ic? analog ground is sensing at the sup- ply? output terminals without interference from ir drops and ground noise. other high-current paths should also be minimized, but focusing primarily on short ground and current-sense connections eliminates about 90% of all pc board layout problems. 2) place the ic and signal components. keep the main switching nodes (lx nodes) away from sensitive analog components (current-sense traces and ref capacitor). place the ic and analog components on the opposite side of the board from the power- switching node. important: the ic must be no more than 10mm from the current-sense resistors. keep the gate-drive traces (dh_, dl_, and bst_) shorter than 20mm and route them away from csh_, csl_, and ref. 3) use a single-point star ground where the input ground trace, power ground (subground plane), and normal ground plane meet at the supply? output ground terminal. connect both ic ground pins and all ic bypass capacitors to the normal ground plane. MAX8741/max8742 sense resistor high-current path figure 9. kelvin connections for the current-sense resistors
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 28 ______________________________________________________________________________________ 2.2 f 5 reset fb5 max8742 pgnd seq ref 11 9 15 12 13 14 20 19 17 16 q3 q4 t2 1:2.2 r2 d5 d2 18 power-good 7 10 8 5v on/off skip dl5 lx5 dh5 bst5 v dd 2.2 f 0.1 f c2 0.1 f 1 f 1n5819 5v output gnd 2.5v ref 3 2 1 24 q1 d1 q2 l1 r1 0.1 f 0.1 f 1n5819 3.3v output (3a) on/off time/on5 run/on3 fb3 28 3v on/off 26 25 27 csl5 csh5 csl3 csh3 dl3 lx3 dh3 bst3 shdn sync input 6.5v to 28v 4 23 22 10 ? 621 v+ v l 0.1 f 0.1 f 4.7 f 4.7 f 12out c3 c1 c4 to 3.3v output to 5v output 12v at 120ma 5v always on figure 10. triple-output application for the max8742
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 29 open MAX8741 v+ shdn v l secfb input 6v to 24v c3 10 ? on/off gnd ref seq sync 1 f 5v always on q1 on/off on/off 0.1 f 0.1 f 4.7 f 4.7 f 0.1 f q3 dl3 csh3 csl3 fb3 reset reset output skip steer l1 r1 5v output c1 dl5 lx5 dh5 bst5 bst3 dh3 lx3 pgnd csl5 csh5 run/on3 time/on5 0 ? fb5 0.1 f 0.1 f l2 r2 3.3v output open 0 ? q4 1n5819 q2 1n5819 c2 figure 11. dual 6a notebook computer power supply
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 30 ______________________________________________________________________________________ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 run/on3 dh3 lx3 bst3 dl3 shdn seq v+ v l pgnd dl5 bst5 lx5 dh5 csh5 csl5 fb5 reset skip ref gnd time/on5 sync v dd 12out fb3 csl3 csh3 ssop max8742 top view ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 run/on3 dh3 lx3 bst3 dl3 shdn seq v+ v l pgnd dl5 bst5 lx5 dh5 csh5 csl5 fb5 reset skip ref gnd time/on5 sync secfb steer fb3 csl3 csh3 MAX8741 32 31 30 29 28 27 26 n.c. fb3 csl3 csh3 run/on3 dh3 lx3 25 n.c. 9 10 11 12 13 14 15 reset fb5 csl5 csh5 seq dh5 lx5 16 n.c. 17 18 19 20 21 22 23 bst5 dl5 pgnd v l v+ shdn dl3 8 7 6 5 4 3 2 skip ref n.c. gnd time/on5 sync secfb MAX8741 thin qfn 5mm 5mm 1 steer 24 bst3 32 31 30 29 28 27 26 n.c. fb3 csl3 csh3 run/on3 dh3 lx3 25 n.c. 9 10 11 12 13 14 15 reset fb5 csl5 csh5 seq dh5 lx5 16 n.c. 17 18 19 20 21 22 23 bst5 dl5 pgnd v l v+ shdn dl3 8 7 6 5 4 3 2 skip ref n.c. gnd time/on5 sync v dd max8742 thin qfn 5mm 5mm 1 12out 24 bst3 pin configurations selector guide device auxiliary output secondary feedback over/undervoltage protection MAX8741 none (secfb input) selectable (steer pin) yes max8742 12v linear regulator feeds into the 5v smps yes
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown ______________________________________________________________________________________ 31 ssop.eps package outline, ssop, 5.3 mm 1 1 21-0056 c rev. document control no. approval proprietary information title: notes: 1. d&e do not include mold flash. 2. mold flash or protrusions not to exceed .15 mm (.006"). 3. controlling dimension: millimeters. 4. meets jedec mo150. 5. leads to be coplanar within 0.10 mm. 7.90 h l 0 0.301 0.025 8 0.311 0.037 0 7.65 0.63 8 0.95 max 5.38 millimeters b c d e e a1 dim a see variations 0.0256 bsc 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 inches min max 0.078 0.65 bsc 0.25 0.09 5.20 0.05 0.38 0.20 0.21 min 1.73 1.99 millimeters 6.07 6.07 10.07 8.07 7.07 inches d d d d d 0.239 0.239 0.397 0.317 0.278 min 0.249 0.249 0.407 0.328 0.289 max min 6.33 6.33 10.33 8.33 7.33 14l 16l 28l 24l 20l max n a d e a1 l c h e n 1 2 b 0.068 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown 32 ______________________________________________________________________________________ qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l e 1 2 21-0140 package outline 16, 20, 28, 32, 40l, thin qfn, 5x5x0.8mm detail b l l1 e
MAX8741/max8742 500khz multi-output power-supply controllers with high impedance in shutdown maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 33 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 e 2 2 21-0140 package outline 16, 20, 28, 32, 40l, thin qfn, 5x5x0.8mm l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. - 40 10 10 5.00 5.00 0.20 0.50 0.40 bsc. 0.40 0.25 4.90 4.90 0.15 0.60 5.10 5.10 0.25 40l 5x5 0.20 ref. 0.75 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 - 0.35 0.45 0.30 0.40 0.50 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 3.40 3.20 3.30 t4055-1 3.20 3.30 3.40 no no no no no no no no yes yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes

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